Pattern recognition via synchronization in phase-locked loop neural networks

Pattern recognition via synchronization in phase-locked loop neural networks

We propose a novel architecture of an oscillatory neural network that consists of phase-locked loop (PLL) circuits. It stores and retrieves complex oscillatory patterns as synchronized states with appropriate phase relations between neurons.

Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

Synchronization Design of a Coupled Phase-Locked Loop

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesti...

Synchronization in networks of mutually delay-coupled phase-locked loops

Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase descriptio...